3D IR-Drop simulation of a complex multilayer PCB

This article deals with the simulation of the voltage drop for complex power delivery networks. Such a simulation is useful to the design engineer in order to ensure the power integrity. With the help of the CST EM STUDIO™ (CST EMS) stationary current solver the 3D distribution of the potential and current density on all layers of a complex PCB board can be easily determined. The static IR-Drop simulation is the primary focus in this article but a dynamic simulation would also be possible in CST MICROWAVE STUDIO®. Before we can start to setup the simulation the PCB board needs to be input.

The multilayer GERBER import was used which is a very general import option that can be linked to all layout/routing tools that can export in GERBER format.

Figure 1: 3D model of the imported PCB (copper only). The z-axis was scaled for demonstration purpose to show the details within such a board.

After the import the material and sources can be defined. In this model input was defined as a fixed potential and all the 96 output ports prescribed a specific current. In reality this represents the current consumed by the ASIC on top of the pins. The option is available to either setup one specific case of input/output or simulate the conductance matrix. This matrix could be used in a circuit simulation in CST DESIGN STUDIO™ (CST DS) to very quickly obtain specific voltage and current information for different situations.

Model setup on the top layer. The power source is shown in red. We used a fixed potential for this source. The 96 output pins are shown in blue and all setup with the same current consumption.

Figure 2: Model setup on the top layer. The power source is shown in red. We used a fixed potential for this source. The 96 output pins are shown in blue and all setup with the same current consumption.

For each simulation the voltage and current at the port is monitored. This allows the voltage drop at a given port to be easily verified. In addition to the scalar potential distribution, CST EMS calculates the electric and current density as vector fields. This helps to decide if the design is reliable or not.

Figure 3: Voltage drop on top layer. Input and output ports are located on this layer.

Figure 4: Voltage drop on ground layer. The source current is routed through vias to this layer from the source to the sink.

This article has briefly demonstrated the use of CST EMS’s stationary current solver for static IR-Drop simulations. Due to the robust meshing technique and the fast solvers, very complex PCBs can be simulated without any approximations in 3D.

This model was provided courtesy of Umberto Gatti, Nokia Siemens Networks S.p.A., Cinisello Balsamo, Italy.

CST Article "3D IR-Drop simulation of a complex multilayer PCB"
last modified 11. Jul 2007 11:45
printed 21. Nov 2008 3:31, Article ID 323
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Article ID: 323 Last modified: 11. Jul 2007 11:45

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