SI and PI
This article describes the use of CST CST MICROWAVE STUDIO® (CST MWS) to solve a coupling problem in a mixed analog – digital multilayer PCB card.
Courtesy and permission of Alvarion, Ltd, Tel-Aviv, Israel.
This example gives an insight into the usefulness of simulation of problems that cannot be investigated easily via measurement and allows the engineer to carry out virtual experiments as demonstrated here with the cutting of the signal trace. Experiments may show the presence of a particular problem but not its location. Even when the problem has been located, further prototypes and experiments are costly and time-consuming. CST MWS offers a straightforward workflow for the set-up and simulation of such problems via its advanced user-interface and EDA interfaces.
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This article concerns the Signal Integrity (SI) analysis of a multi-layered package imported from Cadence® Allegro® via the CST Cadence Link. The typical workflow for setting up and simulating such models in CST MICROWAVE STUDIO® (CST MWS) as well as in CST DESIGN STUDIO™ (CST DS) are presented. Simulated results correlate well with measurements.
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The actual trend in the silicon industry toward higher levels of integration generates chips with densities of tens of millions of transistors. As a consequence, the signal switching frequency in modem digital equipment is beyond the gigahertz range. When the bandwidth requirement increases, the electrical properties of the interconnections affect and limit the integrity of the traveling digital signals.
These phenomena also have an impact on the electromagnetic compatibility (EMC) performance of the system since corrupted signals can easily increase the unwanted electromagnetic interference (EMI).
This article summaries the simulations and measurement carried out using CST MICROWAVE STUDIO® on a multilayered PCB.
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John Contreras and Al Wallash, Hitachi Global Storage Technologies, presentation at the 5th North American Userforum, 2008.
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This article presents the use of CST MICROWAVE STUDIO® (CST MWS) for the simulation of large IC packages. From the time domain simulation network parameters can be extracted and further processed in CST DESIGN STUDIO™.
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This article is concerned with the important issue of Signal Integrity and the application of CST MICROWAVE STUDIO®
to the investigation of the characterisation of an SMA connector on a multi-layer PCB.
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This article demonstrates how CST MICROWAVE STUDIO® has been applied to the Signal Integrity analysis of a multilayer PCB structure. Good agreement with measurement is shown as well as the results for a design suggestion to reduce coupling between planes.
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A physically based method is used for estimating the equivalent circuit
model of an SMA connector soldered on the top plane of a multi-layer board and connected to a single-end stripline. Starting
from the scattering parameters (S-parameters) evaluated using a simulation software package, the equivalent circuit is extracted
by modeling each part of the structure. The circuit is then validated by comparing the outputs obtained via circuit-level simulation
of the extracted physical circuit with those computed by means of the full wave solution.
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An overview is given of the capabilities of the Cadence Allegro import feature in the CST STUDIO SUITE™. The user has full control over the layout export in Cadence itself and during the import process in CST STUDIO SUITE™. Cross-section and packaging export facilitites mean that layers, dies, and bond wires can be specified in the process. The imported structure is also subjected to an automatic cleaning and healing process to ensure an efficient simulation process.
Depending on the size, complexity and required results, either the CST Time-Domain Solver or the Frequency Domain Solver may be used to establish the signal integrity of such layouts.
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A portion of a backplane, designed with the Cadence Allegro® layout tool, is imported into CST MICROWAVE STUDIO®. This section consists of a differential pair with vias which go through the board. The structure was analyzed in Microwave Studio. The simulation results demonstrate the impact of backdrilling the signal vias to improve the signal integrity performance. A detailed SPICE model of the transmission path is created and its accuracy is verified.
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This article summarises the simulation of a System-in-Package (SiP) model using the CST MICROWAVE STUDIO® (CST MWS) Transient Solver to determine the S-Parameters, field distribution and system response when excited with 10 and 20 GHz pulses with additional noise signals. An analysis of the SiP with a board mounting and its effect on the is resonant frequency is also performed. The EMC behaviour of the SiP with and without the mounted board is also considered.
Permission and courtesy of AET Inc. Japan.
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This article deals with the simulation of the voltage drop for complex power delivery networks. Such a simulation is useful to the design engineer in order to ensure power integrity. With the help of the CST EM STUDIO™ stationary current solver the 3D distribution of the potential and current density on all layers of a complex PCB board can be easily determined. The static IR-Drop simulation is the primary focus in this article but a dynamic simulation would also be possible in CST MICROWAVE STUDIO®.
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In this article the simulation of parasitic effects in a standard IC package is shown. The transient simulator in CST MICROWAVE STUDIO® (CST MWS) offers the advantage, that effects such as crosstalk and signal delay can be investigated in both time and frequency domain. Additionally, the simulation results can be used to generate an equivalent RLC network model that has the same S-Parameters as the 3D EM simulation but can be included in the overal circuit simulation of the logical parts of the IC.
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This example shows the simulation of a conductor backed coplanar waveguide with a ground via fence for reducing EMI radiation. The excellent agreement between simulation and simulated results can be observed.
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This article demonstrates the simulatenous excitation of arbitrary waveforms at a number of different ports. A noise source in the form of a loop circuit is place above an IC package and the influence of the noise source on the transmission of differential signals in the IC feed tranmssion lines is investigated. Two frequency ranges were simulated, 1-10 GHz and 1-20 GHz. The simulations were carried out using the simultaneous excitation feature in CST MICROWAVE STUDIO® (CST MWS).
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CST MICROWAVE STUDIO® and Agilent ADS have been successfully employed in this OEIC driver design - an example of a high speed analog/broadband IC application.The package model was imported from Agilent momentum and the model was simulated upto a 100 GHz in CST MWS.The resulting eye diagrams of the driver design from CST MWS are compared with those from Agilent momentum and other test cases.
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The target of this study was to understand the impact of low cost digital (=non-RF) packages on high-speed interface drivers and receivers. The studied low cost package was a 64-pin SQFP with dimensions 10x10 mm2, and with body thickness of 1 mm. The 1.4x1.4 mm2 IC with an active area of 0.01 mm2 was mounted on silicon substrate. The bond wires were of gold, with wire diameter 20 µm with bond pad pitch of 70 µm. The considered package contains the physical layer of a serial high-speed chip-to-chip interface circuit, operating with data rates up to 1 Gbit/s.
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